Novel Hardware Architecture for Fast Address Lookups

The most time critical part in packet forwarding is the route lookup which determines the next hop address of the packet. The problem of searching for routes in large databases is compounded by the fact that routing tables store variable length prefixes and their corresponding next hop addresses. In order to forward a packet, routers need to find the longest matching prefix for the destination address. The work presented here describes a new fast and efficient algorithm for searching a large database. The scheme described here requires several accesses to a small, fast onchip SRAM and only one access to a slower DRAM in order to determine the next hop address. Two main factors motivated this work. The first is the belief that for Gigabiflerabit routing in the future, performing lookups in hardware will be the only altemative. Larger databases make the problem worse because more memory accesses are required to determine the next hop address. Moreover, a large forwarding table cannot be stored in an on-chip memory or a cache and therefore, very expensive off-chip accesses need to be made. The other important factor is the need for a constant lookup time which is especially important for emerging applications like Optical Burst Switching (OBS) that rely on good estimates of time taken from source to destination. If the set-up time at each node is variable, i t would make the delay more unpredictable and would lead to a more inefficient network. Our aim therefore, in designing the forwarding engine was to minimize the off-chip accesses while maintaining a fast, constant lookup time. The rest of the paper is organized as follows. Section I1 discusses some of the related work and approaches in performing route lookups. Section I11 describes our proposed algorithm where only a single off-chip DRAM access is required to determine the next hop address. Section IV discusses some of the details of the hardware implementation and Section V lists some of the results of the scheme. Section VI discusses some of the design issues of the scheme and we finally conclude with Section VII.